1. Field of the Invention
As processors have gotten cheaper, more and more digital data processing systems have appeared in which several processors operate as coprocessors. A coprocessor is a processor which cooperates with another processor to process dam. Classic examples of coprocessors are floating-point units for performing floating point arithmetic and I/O processors for handling the flow of data between peripheral devices such as terminals and the system memory. The relationship between two coprocessors lies along a continuum whose ends are described by the notions tightly coupled and loosely coupled. One coprocessor is tightly coupled to another when there is a high degree of direct interaction between the coprocessors. For example, floating point units are typically tightly coupled. The processor served by the floating point unit provides the operands to the floating point unit, indicates the operation to be performed, and receives the results directly from the floating point unit. The results typically not only include the result value, but also signals indicating the status of the floating point operation. I/O processors, on the other hand, are typically loosely coupled. Communication with the processor they serve is generally through the system memory. When the processor requires the assistance of the I/O processor to output data, the processor places the output data and a description of what the I/O processor is to do with it in memory at a location known to the I/O processor and then indicates to the I/O processor that the data is in memory. The I/O processor thereupon responds to the indication by retrieving the data from memory and outputting it to the desired peripheral device. When it is finished, it puts a record of the status of the operation in memory at a location known to the processor and indicates to the processor that it has finished the memory operation. The processor then responds to the indication by reading the data at the location to determine the status of the output operation.
2. Description of the Prior Art
A problem with memory sharing is that the processors which share the memory must agree on the format of the data which they jointly process. For example, two popular architectures for host processors are the Motorola 680.times.0 architecture and the Intel 80.times.86 architecture. These two architectures have different formats for pointers and for the order in which consecutively written bytes are stored in memory. A coprocessor which is to be used with either kind of host must some how deal with these differences. One way of dealing with them in the prior art has been a pin on the coprocessor whose input indicates whether the host is a 680.times.0 machine or an Intel 80.times.86 machine. This solution works well as long as the coprocessor reads data in exactly the same way as the host wrote it and vice-versa. The problem with such a solution is that it gives the system designer the choice of slowing the coprocessor down or writing code for the coprocessor which is different for the different kinds of hosts. If the coprocessor reads words as well as bytes and the host has written a sequence of bytes in memory, then the fastest way for the coprocessor to read the bytes is as words; however, if it does so, it will have to process the words differently depending on the host machine, and consequently different code will be necessary for the different host machines. Speed and the cost of writing code are both important considerations for the system designer, and consequently both alternatives are unattractive. It is an object of the apparatus disclosed herein to provide a processor which can both read sequences of bytes as words and employ the same code for both host machines.